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KM611001/L
1M x 1Bit High-Speed CMOS SRAM
FEATURES
* Fast Access Time 20, 25, 35ns(Max.) * Low Power Dissipation Standby (TTL) : 40 mA(Max.) (CMOS): 2 mA(Max.) 0.5 mA(Max.) - L-ver. Operating KM611001/L -20 : 130 mA(Max.) KM611001/L -25 : 110 mA(Max.) KM611001/L -35 : 100 mA(Max.) * Single 5.0V 10% Power Supply * TTL Compatible Inputs and Outputs * Fully Static Operation - No Clock or Refresh required * Three State Outputs * Low Data Retention Voltage : 2V(Min.)- L-Ver Only * Standard Pin Configuration KM611001P/LP : 28-DIP-400 KM611001J/LJ : 28-SOJ-400A
CMOS SRAM
GENERAL DESCRIPTION
The KM611001/L is a 1,048,576-bit high-speed Static Random Access Memory organized as 1,048,576 words by 1 bit. The KM611001/L has separate input and output lines for fast read and write access. The device is fabricated using Samsungs advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in highdensity high-speed system applications. The KM611001/L is packaged in a 400 mil 28-pin plastic DIP or SOJ.
FUNCTIONAL BLOCK DIAGRAM
Clk Gen. Pre-Charge Circuit
PIN CONFIGURATION(TOP VIEW)
A0 A1 A2 A3 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 Vcc A19 A18 A17 A16 A15 A14 N.C A13 A12 A11 A10 DIN /CS
A0 A1 Row Select A2 A3 A5 A6 A7 A8 A9 DIN DOUT MEMORY ARRAY 512 Rows 2048x1 Columns
A5 N.C A6 A7 A8 A9 DOUT /WE Vss
SOJ/DIP
22 21 20 19 18 17 16 15
Data Cont. Clk Gen.
I/O Circuit Column Select
PIN DESCRIPTION
A4 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
Pin Name A0-A19 /WE /CS DIN DOUT Vcc Vss N.C
Pin Function Address Inputs Write Enable Chip Select Data Input Data Output Power (+5V) Ground No Connection
/CS
/WE
1
Rev 2.0 July-1996
KM611001/L
ABSOLUTE MAXIMUM RATINGS*
Parameter Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature Operating Temperature Symbol VIN,OUT VCC PD Tstg TA
CMOS SRAM
Rating - 0.5 to 7.0 - 0.5 to 7.0 1.0 - 65 to 150 0 to 70 Unit V V W C C
* Stresses greater than those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA= 0 to 70 C )
Parameter Supply Voltage Ground Input Low Voltage Input High Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.5* Typ. 5.0 0 Max 5.5 0 Vcc+0.5** 0.8 Unit V V V V
* VIL(Min) = -2.0 (Pulse Width 10ns) for I 20mA ** VIH(Max) = VCC+2.0V(Pulse width 10ns) for I 20mA
(TA= 0 to 70 C, VCC=5.0V 10%, unless otherwise specified) Parameter Input Leakage Current Output Leakage Current Operating Current Symbol ILI ILO ICC Test Conditions VIN=Vss to Vcc /CS=VIH or /OE=VIH or /WE=VIL VOUT=VSS to Vcc Min. Cycle, 100% Duty /CS=VIL, VIN=VIH or VIL, IOUT=0mA Standby Current ISB ISB1 Output Low Voltage Output High Voltage VOL VOH Min. Cycle, /CS=VIH f=0MHz, /CS Vcc-0.2V, VIN Vcc -0.2V or VIN 0.2V IOL=8mA IOH = - 4mA Normal L-ver 20ns 25ns 35ns 2.4 130 110 100 40 2 0.5 0.4 V V mA mA mA Min -2 -2 Max 2 2 Unit A A
DC AND OPERATING CHARACTERISTICS
2
Rev 2.0 July-1996
KM611001/L
CAPACITANCE*(f=1MHz, TA =25 C)
Item Input Capacitance Input/Output Capacitance Symbol CIN CI/O Test Condition VIN=0V VI/O=0V
CMOS SRAM
Min. -
Max. 7 7
Unit pF pF
* Note: Capacitance is sampled and not 100% tested.
AC CHARACTERISTICS
TEST CONDITIONS ON DATA RAM(TA= 0 to 70 C, Vcc=5.0V
Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load 10%, unless otherwise specified.) Value 0 to 3 V 3ns 1.5V See below
Output Load (A)
Output Load (B) for tHZ, tLZ, tWHZ, tOW, tOLZ, & tOHZ
+5.0V 480 DOUT 255 30pF* DOUT 255
+5.0V 480
5pF*
* Including Scope and Jig Capacitance
3
Rev 2.0 July-1996
KM611001/L
READ CYCLE
KM611001/L-20 Parameter Read Cycle Time Address Access Time Chip Select to Output Chip Enable to Low-Z Output Chip Disable to High-Z Output Output Hold from Address Change Chip Select to Power Up Time Chip Select to Power Down Time Symbol Min tRC tAA tCO tLZ tHZ tOH tPU tPD 20 5 0 3 0 Max 20 20 12 20 Min 25 5 0 5 0 Max 25 25 15 25 KM611001/L -25
CMOS SRAM
KM611001/L -35 Unit Min 35 5 0 5 0 Max 35 35 15 35 ns ns ns ns ns ns ns ns
WRITE CYCLE
KM611001/L -20 Parameter Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width(/OE High) Write Pulse Width(/OE Low) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Symbol Min tWC tCW tAS tAW tWP tWP tWR tWHZ tDW tDH tOW 20 17 0 17 15 20 2 0 12 0 0 Max 8 Min 25 20 0 20 20 25 3 0 15 0 0 Max 10 Min 35 30 0 30 25 35 3 0 20 0 0 Max 12 ns ns ns ns ns ns ns ns ns ns ns KM611001/L -25 KM611001/L -35 Unit
4
Rev 2.0 July-1996
KM611001/L
TIMING DIAGRAMS
TIMING WAVE FORM OF READ CYCLE(1)
(/CS=VIL, /WE=VIH) tRC Address tAA tOH Data Out Previous Data Valid (Address Controlled)
CMOS SRAM
Data Valid
TIMING WAVE FORM OF READ CYCLE(2)
(/WE=VIH) tRC
Address tAA tCO /CS tOH Data Out High-Z t LZ (4,5) Data Valid tPU 50% tPD 50% t HZ(3,4,5)
Vcc Supply Current
Icc Isb
NOTES (READ CYCLE) 1. /WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ is defined as the time at which the output achieve the open circuit condition and is not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with /CS=VIL 7. Address valid prior to coincident with /CS transition low.
5
Rev 2.0 July-1996
KM611001/L
TIMING WAVE FORM OF WRITE CYCLE(1)
Address tAW tCW(3) /CS tAS(4) /WE tDW High-Z Data In tWHZ Data Out High-Z Data Valid t WP(2) (/WE=Controlled) tRC
CMOS SRAM
t WR(5)
tDH
tOW
TIMING WAVE FORM OF WRITE CYCLE(2)
(/CS=Controlled) tRC
Address tAW tCW(3) /CS t WP(2) /WE tDW High-Z Data In tWHZ Data Out High-Z Data Valid tDH t WR(5)
6
Rev 2.0 July-1996
KM611001/L
NOTES (WRITE CYCLE)
CMOS SRAM
1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition among /CS going low and /WE going low; A write ends at the earliest transition among /CS going high and /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS, or /WE going high. 6. If /CS goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state. 7. Dout is the read data of the new address.
FUNCTIONAL DESCRIPTION
/CS H L L /WE X* H L Mode Not Select Read Write I/O Pin High-Z DOUT DIN Supply Current ISB, ISB1 ICC ICC
*Note : X means Don't Care.
DATA RETENTION CHARACTERISTICS*(TA= 0
Parameter Vcc for Data Retention Data Retention Current Data Retention Set-Up Time Recovery Time * L-version only Symbol VDR IDR tSDR tRDR /CS Vcc-0.2V
to 70 C) Min. 2.0 0 5 Typ. Max. 5.5 0.1 Unit V mA ns ms
Test Condition Vcc=3.0V, /CS Vcc-0.2V VIN Vcc-0.2V or VIN 0.2V See Data Retention Wave form(below)
DATA RETENTION WAVE FORM
tSDR Vcc 4.5V 2.2V VDR
(/CS Controlled) tRDR Data Retention Mode
/CS GND
/CS Vcc-0.2V
7
Rev 2.0 July-1996
KM611001/L
PACKAGE DIMENSIONS
28-SOJ-400A
#28
CMOS SRAM
Unit: mm / Inch
18.82 Max. 0.741 3.76 Max. 0.148 18.42 0.12 0.725 0.005
0.69 Min. 0.027
0.10 Max. 0.004 Max.
0.95 0.037
+0.10 0.43 -0.05 0.017 +0.004 -0.002 +0.10 0.71 -0.05 0.028 +0.004 -0.002
1.27 0.050
28-DIP-400
#28
9.09 0.20 0.358 0.008 10.16 0.400
0 ~ 15
+0.10 0.25 -0.05 0.010 +0.004 -0.002
#1
35.96 Max. 1.46 35.56 0.20 1.400 0.008 4.32 0.20 0.170 0.008
0.51 Min. 0.020
1.27 0.050
1.27 0.10 0.050 0.004 0.46 0.10 0.018 0.004
2.54 0.100
*Note : Do not include mold protrusion
8 Rev 2.0 July-1996
3.18 0.30 0.125 0.012
5.08 Max. 0.200
+ 0.10 0.20 - 0.05 0.008 + 0.004 - 0.002
#1
9.40 0.25 0.370 0.010
11.18 0.12 0.440 0.005
10.16 0.400

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